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MITSUBISHI
M56692FP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
DESCRIPTION
The M56692FP is a semiconductor integrated circuit that has a built-in, 32-bit shift register and a latch of CMOS structure with serial input and serial/parallel output, and a 32-bit totem-pole-type parallel output driver of high pressure proof DMOS structure. Employed are Bi-CMOS and high pressure proof DMOS processing technology.
PIN CONFIGURATION (TOP VIEW)
33 HVO22
32 HVO21
31 HVO20
30 HVO19
29 HVO18
28 HVO17
27 HVO16
26 HVO15
25 HVO14
24 HVO13
FEATURES
q Serial input - serial/parallel output q Bidirectional shift register (controlled at F/R terminal) q Cascade connections possible through serial output. q Latch circuit included for each stage. q Driver supply voltage: VH=90V q Operating temperature: -40 - 85C
HVO23 HVO24 HVO25 HVO26 HVO27 HVO28 HVO29 HVO30 HVO31 HVO32 PGND
23 HVO12 22 HVO11 21 HVO10 20 HVO 9 19 HVO 8 18 HVO 7 17 HVO 6 16 HVO 5 15 HVO 4 14 HVO 3 13 HVO 2 12 HVO 1
34 35 36 37 38 39 40 41 42 43 44
M56692FP
Vacuum Fluorescent Display GRID DRIVER
BLOCK DIAGRAM
HVO 1 12
HVO 2 13
HVO 3 14
HVO30 41
HVO31 42
Output protect circuit
VH SOUT(SIN) VDD F/R LGND CLK LAT BLK SIN(SOUT)
APPLICATION
Outline 44P6N-A
HVO32 43 1 10
VH 10 PGND 11
1
2
3
4
5
6
7
8
9
VH
VDD
3 11 PGND
BLK 8 Q LGND LAT 5 LD Q LD Q LD Q LD Q LD Q LD
44
7
SIN (SOUT)
9
DQ T
DQ T
DQ T
DQ T
DQ T
DQ T
2
SOUT (SIN)
CLK
6 4 F/R
3-58
MITSUBISHI
M56692FP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
Serial-output SOUT is used by connecting to the next stage M56692FP SIN when more than one M56692FP is used to expand bits in the series. In accordance with truth table 2, parallel output allows the latch to pass data through if LAT input is turned to "H", and data to be retained if LAT input is turned to "L". Driver output HVOn allows data from the latch to be output if BLK input is turned to "L", and "L" to be output if BLK input is turned to "H" irrespective of data from the latch.
FUNCTION
The M56692FP comprises a 32 bit bidirectional shift register, a 32 bit latch, and a parallel output HVO 1 - HVO32 connected to its output. In accordance with truth table 1, the data transfer direction of shift register depends upon F/R input, and F/R being at "H" or open allows pin 9 to turn to SIN and pin 2 to turn to SOUT, and F/R being at "L" allows pin 2 to turn to SIN and pin 9 to turn to SOUT, permitting data transfer from SIN to SOUT, respectively. Inputting data to SIN and clock pulse to CLK allows SIN signal to be put into the internal shift register when the clock changes from "H" to "L", and shift register data to be shifted sequentially.
TRUTH TABLE Truth table 1. Shift register section
Input F/R H H L L CLK H or L H or L Input/output Shift register SIN(SOUT) IN IN OUT OUT SOUT(SIN) OUT OUT IN IN DATA is shifted. No changes. DATA is shifted. No changes.
Truth table 2. Latch and driver sections
Dn X H L X LAT X H H L BLK H L L L HVOn Output all "L" H L Latch's data output. Dn=nth bit DFF retention data HVOn=nth bit driver output L = "L" level H = "H" level X = "L" level or "H" level
PIN FUNCTION DESCRIPTION
Pin name VDD LGND VH PGND CLK SIN SOUT LAT BLK F/R HVO1-32 Function Logic stage supply voltage Logic stage ground Output stage supply voltage Output stage supply ground Clock input for the internal shift resister. The data enter the internal shift resisters and the data in the shift registers will be shifted in order by High to Low change of the clock. Serial data input Serial data output Latch input. When the LATCH is set to "H", the data in the shift resister will enter the each latch circuit. When the LATCH input is set to "L", the data will be held. Enable input for output control. When the BLK input is set to "L", data in the latch circuit will appear at outputs. When the BLK input is set to "H", all outputs will be set to "L". Direction Control for the internal shift resister Output driver (push-pull)
ABSOLUTE MAXIMUM RATINGS (Ta=25C, unless otherwise noted)
Symbol VDD VH VI VO VHVO Pd Tstg Parameter Logic stage supply voltage Output stage supply voltage Logic inputs voltage Logic output voltage Output voltage Power dissipation range Storage temperature range Conditions Ratings -0.3 - 7 -0.3 - 90 -0.3 - VDD+0.3 -0.3 - VDD+0.3 -0.3 - VH 850 -55 - 150 Unit V V V V V mW C
Data output High supply voltage output pin Ta 25C
MITSUBISHI
M56692FP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VH Topr Parameter Supply voltage Supply voltage Operating temperature Conditions Ratings 4-6 40 - 90 -40 - 85 Unit V V C
ELECTRICAL CHARACTERISTICS (VDD=5V, VH=80V and Ta=25C, unless otherwise noted)
Symbol IDD IH IIH IIL VHVOH VHVOL VOH VOL IHVOH IHVOL VTH VTL Parameter Supply current 1 Supply current 2 "H" input current "L" input current Driver output voltage Logic output voltage "H" output current "L" output current Output protect operating voltage No load Output all "L", no load 1 bit "H", no load VIH=5V input pin VIL = 0V SIN, LAT, CLK BLK, F/R 70 4.5 Test conditions Min. Limits Typ. 0.4 0 0.4 0 0 -250 75.5 0.5 4.9 0.1 -50 10 3.3 3.0 Max. 2 1 1 1 -1 -500 2.5 0.4 -100 20 Unit mA mA mA A A A V V mA mA V V
IHVOH = -50mA IHVOL = 10mA IOH = -0.1mA IOL = 0.1mA Duty cycle 2.5%*
* Maximum numbers of Outputs High State are two at the same time.
SWITCHING CHARACTERISTICS (VDD=5V, VH=80V and Ta=25C, unless otherwise noted)
Symbol fCLK t PLH(SO) t PHL(SO) t PLH(OUT) t PHL(OUT) trout tfout Parameter Clock frequency Logic output propagation time Driver output propagation time Driver output rise and fall time Test conditions Duty = 45 - 55% CL = 15pF 90 60 95 70 35 65 Min. Limits Typ. Max. 8 180 180 Unit MHz ns ns ns ns ns ns
RO = 220K CO = 50pF
TEST CIRCUIT
INPUT VDD VH (1) Characteristics of pulse generator (PG) tr20ns tf20ns (2) Capacitance CL includes connection floating capacitance and probe input capacitance. : RO=220K : CO=50pF
SOUT PG DUT CL HVOn 50
CO
RO
MITSUBISHI
M56692FP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
TIMING WAVEFORM
1/fmax CLK
50% 50% 50%
SIN
50%
50%
tsu tfso SOUT
90% 50% 10% 10%
th trso
90% 50%
tPHL(SO)
tPLH(SO)
BLK
50%
50%
trOUT HVOn
10% 90% 50% 90% 50%
tfOUT
10%
tPLH(OUT)
tPHL(OUT)
MITSUBISHI
M56692FP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
TYPICAL CHARACTERISTICS
Thermal derating
1.0 -100 Ta=-40C "H" output current IOH(mA) Power dissipation Pd(W) 0.8 -80 Ta=85C
Driver output VON-IOH
Ta=25C
0.6
-60
0.4
-40
0.2
-20
0.0 0 25 50 75 100 125 Temperature Ta (C) 150
0
0
2
4
6
8
10
12
"H" output ON voltage VON (V)
Duty cycle vs Permissible output current
100 90 Output current IOH(mA) Output current IOH(mA) 80 70 60 50 40 30 20 10 0 0 20 40 60 80 100 Duty cycle (%)
16 24 32 8 4 2 1
Duty cycle vs Permissible output current
100 90 80 70 60
2 1
50 40 30 20 10 0 0 20 40 60 Duty cycle (%)
32 4
8 16 24
80
100
Note
* Ta=25C * Repeated frequency>100Hz * Figure in the circle represents the number of concurrently operating output circuits. * Current value denotes a numerical value per circuit.
Note
* Ta=85C * Repeated frequency>100Hz * Figure in the circle represents the number of concurrently operating circuits. * Current value denotes a numerical value per circuit.
(Note) 1. VDD=5V and VH=80V unless otherwise noted. 2. Thermal derating curve represents that of an individual IC unit. 3. Allowable duty cycle output curve represents that when a standard substrate is mounted. (Standard substrate: 70x70x1.6mm glass epoxy)

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